1. Field of the Invention
The present invention relates to a method for manufacturing an asymmetrical lightly-doped drain (LDD) type metal oxide semiconductor (MOS, broadly, MIS) device.
2. Description of the Related Art
In a fine-structured MOS device, in order to avoid deterioration of characteristics due to hot carriers, an LDD structure has been broadly used.
A prior art LDD type MOS device is constructed by a gate electrode via a gate silicon oxide layer on a P-type monocrystalline silicon substrate, sidewall silicon oxide layers on both sides of the gate electrode, N.sup.- -type impurity diffusion regions within the substrate beneath the sidewall silicon oxide layers, and N.sup.+ -type impurity diffusion regions within the substrate outside of the N.sup.- -type impurity diffusion regions. In this case, one of the N.sup.- -type impurity diffusion regions and one of the N.sup.+ -type diffusion regions adjacent to each other serve as a drain, and the other of the N.sup.- -type impurity diffusion regions and the other of the N.sup.+ -type impurity diffusion regions adjacent to each other serve as a source. Since the drain and source are symmetrical, this device is called a symmetrical LDD-type MOS device. This will be explained later in detal.
In the above-mentioned prior art symmetrical LDD type MOS device (transistor), however, since the N.sup.- -type impurity diffusion region is present on the source region, even when the MOS transistor is turned ON, the amount of carriers, i.e., electrons injected into a channel region is small, so that the ON current becomes small. Also, when this symmetrical LDD type MOS transistor is applied to one static random access memory (SRAM) cell, the presence of two N.sup.- -type impurity diffusion regions between two gates of driving transistors increases the distance therebetween, to reduce the integration.
On the other hand, generally, the reliability of a MOS transistor, i.e., the reduction of an ON current by hot carriers is dependent upon a drain structure, and therefore, the N.sup.- -type impurity diffusion region within the source region does not contribute to the enhancement of the reliability. In other words, it is preferable that the N.sup.- -type impurity diffusion region is absent from the source region. Therefore, in order to improve the symmctrical LDD type MOS transistor, an asymmetrical LDD type MOS transistor has been known (see JP-A-HEI2-158143).
In a prior art method for manufacturing an asymmetrical LDD type MOS transistor, N.sup.- -type impurity diffusion regions are formed within a semiconductor substrate on both sides of a gate electrode. Then, a photoresist pattern layer is formed to cover one of the N.sup.- -type impurity regions on the drain region, and thereafter, impurities such as arsenic are further implanted into the N.sup.- -type impurity diffusion region on the source region side. As a result, the N.sup.- -type impurity diffusion region on the source region side is converted into an N.sup.+ -type impurity diffusion region. Then, sidewall silicon oxide layers are formed on both sides of the gate electrode, and after that, impurities such as arsenic are implanted. As a result, an N.sup.+ -type impurity diffusion region is formed adjacent to the N.sup.- -type impurity diffusion region on the drain region side. This will be explained later in detail.
In the above-mentioned prior art method for manufacturing an asymmetrical LDD type MOS transistor, however, an additional photolithography process for forming the N.sup.+ -type impurity diffusion region on the source region side is required which increases the manufacturing cost. Also, high concentration ion implantation processes are increased to invite charging-up of charges (electrons) within the substrate and destruction of the gate silicon oxide layer.